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VIPER20

VIPER20资料
VIPER20
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File Size : 116 KB
Manufacturer:STM
Description:The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offCstate condition when calculating td(on) and is read at a voltage corresponding to the onCstate when calculating td(off).   At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified.   The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.
 
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型 号:VIPER20
厂 家:STM
封 装:TO220-5
批 号:08+
数 量:3500
说 明:全新原装,长期稳定供应
 
 
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