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| VB025MSP13TR资料 | |
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VB025MSP13TR PDF Download |
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File Size : 116 KB
Manufacturer:STM Description:A LOW signal on MR overrides the Select and CP inputs and resets the flip-flops. All other state changes are initi- ated by the rising edge of the clock. Inputs can change when the clock is in either state provided only that the rec- ommended setup and hold times, relative to the rising edge of CP, are observed. A HIGH signal on either OE1 or OE2 disables the 3-STATE buffers and puts the I/O pins in the high impedance state. In this condition the shift, hold, load and reset operations can still occur. The 3-STATE buffers are also disabled by HIGH signals on both S0 and S1 in preparation for a paral- lel load operation. |
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| 1PCS | 100PCS | 1K | 10K | ||
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型 号：VB025MSP13TR 厂 家：STM 封 装：08+ 批 号：SOP-10 数 量：136991 说 明：全新原装，长期稳定供应 |
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运 费： 所在地： 新旧程度： |
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| 电 话：086-755-23815997 |
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