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TS954I

TS954I资料
TS954I
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File Size : 116 KB
Manufacturer:STM
Description:During the byte-load cycle, the addresses are latched by the falling edge of either #CE or #WE, whichever occurs last. The data are latched by the rising edge of either #CE or #WE, whichever occurs first. If the host loads a second byte into the page buffer within a byte-load cycle time (TBLC) of 200 µS, after the initial byte-load cycle, the W29EE512 will stay in the page load cycle. Additional bytes can then be loaded consecutively. The page load cycle will be terminated and the internal programming cycle will start if no additional byte is loaded into the page buffer A7 to A15 specify the page address. All bytes that are loaded into the page buffer must have the same page address. A0 to A6 specify the byte address within the page. The bytes may be loaded in any order; sequential loading is not required.
 
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型 号:TS954I
厂 家:STM
封 装:SOP
批 号:08+
数 量:600
说 明:全新原装,长期稳定供应
 
 
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