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| TLP624-3资料 | |
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TLP624-3 PDF Download |
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File Size : 116 KB
Manufacturer:TOS Description:The CY7C133 (master) provides on-chip arbitration to resolve simultaneous memory location access (contention). Table 2 shows a summery of conditions where BUSY is asserted. If both ports CEs are asserted and an address match occurs within tPS of each other, the busy logic will determine which port has access. If tPS is violated, one port will definitely gain permission to the location, but which one is not predictable. BUSY will be asserted tBLA after an address match or tBLC after CE is taken LOW. The results of all eight arbitration possibilities are summarized in Table 3. BUSY is an open drain output and requires a pull-up resistor. |
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型 号：TLP624-3 厂 家：TOS 封 装：DIP/SOP 批 号：07+ 数 量：2000 说 明：全新库存，专业TOSHIBA供应商 |
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