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| TLP3521资料 | |
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TLP3521 PDF Download |
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File Size : 116 KB
Manufacturer:TOS Description:Lowest power 384 macrocell CPLD 7.5 ns pin-to-pin logic delays System frequencies up to 127 MHz 384 macrocells with 9,600 usable gates Available in small footprint packages - 144-pin TQFP (118 user I/O) - 208-pin PQFP (172 user I/O) - 256-ball FBGA (212 user I/O) - 324-ball FBGA (220 user I/O) Optimized for 3.3V systems - Ultra low power operation - 5V tolerant I/O pins with 3.3V core supply - Advanced 0.35 micron five layer metal EEPROM process - FZP™ CMOS design technology Advanced system features - In-system programming - Input registers - Predictable timing model - Up to 23 clocks available per function block - Excellent pin retention during design changes - Full IEEE Standard 1149.1 boundary-scan (JTAG) - Four global clocks - Eight product term control terms per function block Fast ISP programming times Port Enable pin for additional I/O |
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| 1PCS | 100PCS | 1K | 10K | ||
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型 号：TLP3521 厂 家：TOS 封 装：DIP/SOP 批 号：07+ 数 量：2000 说 明：全新库存，专业TOSHIBA供应商 |
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运 费： 所在地： 新旧程度： |
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| 联系人：林小姐 |
| 电 话：086-755-23815997 |
| 手 机：13632589437 |
| QQ：1097182423,2851921558 |
| MSN： |
| 传 真：0755-23815984 |
| EMail：joylin@hongbotong.com |
| 公司地址： 深圳市福田区深南中路3006号佳和大厦B座2007室 |
