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| NCS2553DR2G资料 | |
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NCS2553DR2G PDF Download |
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File Size : 116 KB
Manufacturer:ON Description:The two RAMs in any CLB can be changed to synchronous write operation. In this synchronous mode, the internal write operation is controlled by the same clock that drives the flip-flops. The clock polarity is programmable for the RAM (both F and G function generators together), but is independent of the chosen flip-flop polarity. Address, Data, and WE inputs are latched by this rising or falling clock edge, and a short internal write pulse is generated right after the clock edge. This self-timed write operation is thus effectively edge-triggered. |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：NCS2553DR2G 厂 家：ON 封 装：SOP-8 批 号：07+ 数 量：150000 说 明：原装正品，大量供应 |
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运 费： 所在地： 新旧程度： |
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| 联系人：林小姐 |
| 电 话：086-755-23815997 |
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