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LM4811MM资料 | |
LM4811MM PDF Download |
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File Size : 116 KB
Manufacturer:NS Description:Notes: 2. X =Don't Care. H = Logic HIGH, L = Logic LOW. BWx = 0 signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired byte write selects are asserted, see truth table for details. 3. Write is defined by BW[A:B], and WE. See truth table for Read/Write. 4. When a write cycle is detected, all I/Os are three-stated, even during byte writes. 5. The DQs and DQP[A:B] pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 6. CEN = H, inserts wait states. 7. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE. 8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP[A:B] = Three-state when OE is inactive or when the device is deselected, and DQs and DQP[A:B] = data when OE is active. |
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1PCS | 100PCS | 1K | 10K | ||
价 格 | |||||
型 号:LM4811MM 厂 家:NS 封 装:SSOP 批 号:06+ 数 量:15000 说 明:全新原装大量长期供应 |
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