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| LCA210L资料 | |
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LCA210L PDF Download |
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File Size : 116 KB
Manufacturer:CLARE Description: The MC100EP139 is a low skew 2/4, 4/5/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differential or singleCended ECL or, if positive power supplies are used, LVPECL input signals. In addition, by using the VBB output, a sinusoidal source can be AC coupled into the device. If a singleCended input is to be used, the VBB output should be connected to the CLK input and bypassed to ground via a 0.01µF capacitor. The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. The internal enable flipCflop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. Upon startup, the internal flipCflops will attain a random state; therefore, for systems which utilize multiple EP139s, the master reset (MR) input must be asserted to ensure synchronization. For systems which only use one EP139, the MR pin need not be exercised as the internal divider design ensures synchronization between the 2/4 and the 4/5/6 outputs of a single device. All VCC and VEE pins must be externally connected to power supply to guarantee proper operation. |
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| 1PCS | 100PCS | 1K | 10K | ||
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型 号：LCA210L 厂 家：CLARE 封 装：DIP/SOP 批 号：07+ 数 量：2000 说 明：全新库存，专业光耦继电器供应商 |
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运 费： 所在地： 新旧程度： |
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| 联系人：林小姐 |
| 电 话：086-755-23815997 |
| 手 机：13632589437 |
| QQ：1097182423,2851921558 |
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| 传 真：0755-23815984 |
| EMail：joylin@hongbotong.com |
| 公司地址： 深圳市福田区深南中路3006号佳和大厦B座2007室 |
