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| L9132资料 | |
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L9132 PDF Download |
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File Size : 116 KB
Manufacturer:STM Description:The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Readback will support standard SMBUS controller protocol. The number of bytes to readback is defined by writing to byte 8. When writing to byte 11 - 12, and byte 13 - 14, they must be written as a set. If for example, only byte 14 is written but not 15, neither byte 14 or 15 will load into the receiver. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only Block-Writes from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown. |
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| 1PCS | 100PCS | 1K | 10K | ||
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型 号：L9132 厂 家：STM 封 装：08+ 批 号： 数 量：8750 说 明：全新原装，长期稳定供应 |
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运 费： 所在地： 新旧程度： |
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| 联系人：林小姐 |
| 电 话：086-755-23815997 |
| 手 机：13632589437 |
| QQ：1097182423,2851921558 |
| MSN： |
| 传 真：0755-23815984 |
| EMail：joylin@hongbotong.com |
| 公司地址： 深圳市福田区深南中路3006号佳和大厦B座2007室 |
