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| HCPL-4N26资料 | |
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HCPL-4N26 PDF Download |
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File Size : 116 KB
Manufacturer:AGILENT Description:A debounced RESET input is provided. Connecting the RESET input to VDD resets the 12 low-order stages of the frequency divider, thus disabling further motor pulses. Motor pulses, which are in progress when the reset function is applied, will be completed. After releasing the RESET pad from VDD, the next motor pulse appears with a delay of one half motor cycle on the drive output opposed to the former (Figure 4). Due to the debounce circuitry on the RESET input, VDD must be applied for at least 31.2 ms. Dur- ing RESET the input current is limited to 8 nA typically. |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：HCPL-4N26 厂 家：AGILENT 封 装：DIP/SOP 批 号：05+ 数 量：2000 说 明：全新库存，专业AVAGO光耦供应商 |
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| 联系人：林小姐 |
| 电 话：086-755-23815997 |
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