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| HCPL-4717资料 | |
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HCPL-4717 PDF Download |
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File Size : 116 KB
Manufacturer:AGILENT Description:The Self Refresh allows the user a dynamic refresh, data retention mode at the extended refresh period of 128 ms. i.e., 125 µs per row when using distributed CBR refreshes. The feature also allows the user the choice of a fully static, low power data retention mode. The optional Self Refresh feature is initiated by performing a CBR Refresh cycle and holding RAS LOW for the specified tRASS. The Self Refresh mode is terminated by driving RAS HIGH for a minimum time of tRPS. This delay allows for the completion of any internal refresh cycles that may be in process at the time of the RAS LOW-to-HIGH transition. If the DRAM controller uses a distributed refresh sequence, a burst refresh is not required upon exiting Self Refresh. However, if the DRAM controller utilizes a RAS-only or burst refresh sequence, all 1,024 rows must be refreshed within the average internal refresh rate, prior to the re- sumption of normal operation. |
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| 1PCS | 100PCS | 1K | 10K | ||
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型 号：HCPL-4717 厂 家：AGILENT 封 装：DIP/SOP 批 号：05+ 数 量：2000 说 明：全新库存，专业AVAGO光耦供应商 |
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