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| HCPL-2562资料 | |
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HCPL-2562 PDF Download |
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File Size : 116 KB
Manufacturer:AGILENT Description:Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the Active command are used to select the bank and row to be accessed. The address bits registered coincident with the Read or Write command are used to select the bank and the starting column location for the burst access. |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：HCPL-2562 厂 家：AGILENT 封 装：DIP/SOP 批 号：05+ 数 量：2000 说 明：全新库存，专业AVAGO光耦供应商 |
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运 费： 所在地： 新旧程度： |
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| 联系人：林小姐 |
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