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| DWA101N资料 | |
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DWA101N PDF Download |
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File Size : 116 KB
Manufacturer: Description:DRQ DMA Request (Output, active High). This signal is asserted when the chip is ready to transfer a data byte to and from the DMA controller. The DMA Request will be asserted only if the DMA Mode bit (Register 2, Bit 1) is set. The transfer is complete upon reception of /DACK. |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：DWA101N 厂 家： 封 装：DIP16 批 号：06+ 数 量：1260 说 明：全新原装正品,优势库存热卖中! |
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运 费： 所在地： 新旧程度： |
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