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BTS131

BTS131资料
BTS131
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File Size : 116 KB
Manufacturer:INF
Description:The C6711/C6711B/C6711C/C6711D uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 32-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 32-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 512-Kbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM, SBSRAM and asynchronous peripherals.
 
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型 号:BTS131
厂 家:INF
封 装:08+
批 号:TO220 TO263
数 量:24553
说 明:全新原装,长期稳定供应
 
 
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