SN74LV595A的技术资料

SN74LV595A的产品特征：
* 2-V to 5.5-V V_CC Operation
* Max tpd of 7.1 ns at 5 V
* Typical V_OLP (Output Ground Bounce)
   <0.8 V at V_CC = 3.3 V, TA = 25℃
* Typical V_OHV (Output VOH Undershoot)
   >2.3 V at V_CC = 3.3 V, TA = 25℃
* Support Mixed-Mode Voltage Operation on
   All Ports
* 8-Bit Serial-In, Parallel-Out Shift
* Ioff Supports Partial-Power-Down Mode
   Operation
* Shift Register Has Direct Clear
* Latch-Up Performance Exceeds 250 mA Per
   JESD 17
* ESD Protection Exceeds JESD 22
   − 2000-V Human-Body Model (A114-A)
   − 200-V Machine Model (A115-A)
   − 1000-V Charged-Device Model (C101)

SN74LV595A的技术参数：
Supply voltage range, V_CC  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . .−0.5 V to 7 V
Input voltage range, V_I (see Note 1)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . .−0.5 V to 7 V
Voltage range applied to any output in the high-impedance
   or power-off state, V_O (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .−0.5 V to 7 V
Output voltage range applied in the high or low state, V_O (see Notes 1 and 2) . . . . . . −0.5 V to V_CC + 0.5 V
Input clamp current, I_IK (V_I < 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
Output clamp current, I_OK (V_O < 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . −50 mA
Continuous output current, I_O (V_O = 0 to V_CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±35 mA
Continuous current through V_CC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±70 mA
Package thermal impedance, θ_JA (see Note 3): D package  . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . .73℃/W
                                                    (see Note 3): DB package  . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .82℃/W
                                                    (see Note 3): NS package  . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . .64℃/W
                                                    (see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108℃/W
                                                    (see Note 4): RGY package  . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . .39℃/W
Storage temperature range, T_stg. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . −65℃ to 150℃

SN74LV595A的产品描述：

The ’LV595A devices are 8-bit shift registers designed for 2-V to 5.5-V V_CC operation.

These devices contain an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and a serial output for cascading. When the output-enable (OE) input is high, all outputs except QH′ are in the high-impedance state.

Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both clocks are connected together, the shift register always is one clock pulse ahead of the storage register.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.